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cy23s09, cy23s05 low cost 3.3 v spread aware zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07296 rev. *g revised october 04, 2011 features 10 mhz to 100 mhz and 133 mhz operating range, compatible with cpu and pci bus frequencies zero input-output propagation delay multiple low skew outputs ? output-output skew less than 250 ps ? device-device skew less than 700 ps ? one input drives five outputs (cy23s05) ? one input drives nine outputs, grouped as 4 + 4 + 1 (cy23s09) less than 200 ps cycle-to-cycle jitter is compatible with pentium based systems test mode to bypass pll (cy23s09 only, see select input decoding for cy23s09 on page 2) available in space saving 16-pin, 150-mil soic, 4.4 mm tssop, and 150-mil ssop (cy23s09) or 8-pin, 150-mil soic package (cy23s05) 3.3 v operation, advanced 0.65 ? cmos technology spread aware functional description the cy23s09 is a low cost 3.3 v zero delay buffer designed to distribute high speed clocks and is available in a 16-pin soic package. the cy23s05 is an 8- pin version of the cy23s09. it accepts one reference input, and drives ou t five low skew clocks. the -1h versions of each device operate at up to 100 and 133 mhz frequencies and have higher drive than the -1 devices. all parts have on-chip plls that lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. the cy23s09 has two banks of four outputs each, which can be controlled by the select inputs as shown in the select input decoding table on select input decoding for cy23s09 on page 2. if all output clocks are not required, bank b can be three-stated. the select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. the cy23s09 and cy23s05 plls enter a power down mode when there are no rising edges on the ref input. in this state, the outputs are three-stated and the pll is turned off, resulting in less than 12.0 ? a of current draw (for commercial temperature devices) and 25.0 ? a (for industrial tem perature devices). the cy23s09 pll shuts down in one additional case, as shown in the select input decoding for cy23s09 on page 2. multiple cy23s09 and cy23s05 devices can accept the same input clock and distribute it. in this case, the skew between the outputs of two devices is guara nteed to be less than 700 ps. all outputs have less than 200 ps of cycle-to-cycle jitter. the input to output propagation delay on both devices is guaranteed to be less than 350 ps; the output to output skew is guaranteed to be less than 250 ps. the cy23s05 and cy23s09 is available in two different config- urations, as shown in the ordering information on page 7. the cy23s05-1 and cy23s09-1 is the base part. the cy23s05-1h and cy23s09-1h is the high drive version of the -1, and its rise and fall times are much faster than -1. logic block diagram
cy23s09, cy23s05 document number: 38-07296 rev. *g page 2 of 12 figure 1. ref. input to clka/clkb delay vs. loading difference between clkout and clka/clkb pins zero delay and skew control all outputs must be uniformly loaded to achieve zero delay between the input and output. because the clkout pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. this is shown in the above graph. for applications requiring zero input-output delay, all outputs, including clkout, must be equally loaded. even if clkout is not used, it must have a capaciti ve load equal to that on other outputs, to obtain zero input-output delay. if input to output delay adjustments are required, use the above graph to calculate loading differences between the clkout pin and other outputs. for zero output-output skew, be sure to load all outputs equally. for further information, see application note ?an1234 - cy2308: zero delay buffer.? spread aware many systems being designed now use a technology called spread spectrum frequency timi ng generation. cypress is one of the pioneers of ssftg development and designed this product so as not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass the ss feature through, the result is a signif- icant amount of tracking skew, which may cause problems in systems requiring syn chronization. for more details on spread spectrum timing technology, please see the cypress whitepaper emi and spread spectrum technology. select input decoding for cy23s09 s2 s1 clock a1?a4 clock b1?b4 clkout [1] output source pll shutdown 0 0 three-state three-state driven pll n 0 1 driven three-state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n note 1. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and output.
cy23s09, cy23s05 document number: 38-07296 rev. *g page 3 of 12 pinouts figure 2. pin configuration ? cy23s09 figure 3. pin configuration ? cy23s05 table 1. pin description for cy23s09 pin signal description 1ref [2] input reference frequency, 5 v tolerant input 2 clka1 [3] buffered clock output, bank a 3 clka2 [3] buffered clock output, bank a 4v dd 3.3 v supply 5 gnd ground 6 clkb1 [3] buffered clock output, bank b 7 clkb2 [3] buffered clock output, bank b 8s2 [4] select input, bit 2 9s1 [4] select input, bit 1 10 clkb3 [3] buffered clock output, bank b 11 clkb4 [3] buffered clock output, bank b 12 gnd ground 13 v dd 3.3 v supply 14 clka3 [3] buffered clock output, bank a 15 clka4 [3] buffered clock output, bank a 16 clkout [3] buffered output, internal feedback on this pin table 2. pin description for cy23s05 pin signal description 1ref [2] input reference frequency, 5 v tolerant input 2clk2 [3] buffered clock output 3clk1 [3] buffered clock output 4 gnd ground 5clk3 [3] buffered clock output 6v dd 3.3 v supply 7clk4 [3] buffered clock output 8 clkout [3] buffered clock output, internal feedback on this pin notes 2. weak pull down. 3. weak pull down on all outputs. 4. weak pull up on these inputs.
cy23s09, cy23s05 document number: 38-07296 rev. *g page 4 of 12 maximum ratings supply voltage to ground potenti al ...............?0.5 v to +7.0 v dc input voltage (except ref) .......... ?0.5 v to v dd + 0.5 v dc input voltage ref ???????????????????????????????????????????? ? 0.5 v to 7 v storage temperature ................................ ?65 ? c to +150 ? c maximum soldering temperature (10 seconds) ......... 260 ? c junction temperature................................................. 150 ? c static discharge voltage (per mil-std-883, method 3015) .. ............. ........... > 2,000 v operating conditions for cy 23s05sc-xx and cy23s09sc-xx commercial temperature devices [5] parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (a mbient temperature) 0 70 ? c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 7 pf electrical characteristics for cy 23s05sc-xx and cy23s09sc-xx commercial temperature devices parameter description test conditions min max unit v il input low voltage [6] 0.8 v v ih input high voltage [6] 2.0 v i il input low current v in = 0 v 50.0 ? a i ih input high current v in = v dd 100.0 ? a v ol output low voltage [7] i ol = 8 ma (?1) i oh = 12 ma (?1h) 0.4 v v oh output high voltage [7] i oh = ?8 ma (?1) i ol = ?12 ma (?1h) 2.4 v i dd (pd mode) power-down supply current ref = 0 mhz 12.0 ? a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v dd 32.0 ma switching characteristics fo r cy23s05sc-1 and cy23s09sc-1 commercial temperature devices [8] parameter description test conditions min typ max unit t1 output frequency 30 pf load 10 pf load 10 10 100 133.33 mhz mhz duty cycle [7] = t 2 ? t 1 measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % t3 rise time [7] measured between 0.8 v and 2.0 v 2.50 ns t 4 fall time [7] measured between 0.8 v and 2.0 v 2.50 ns t 5 output-to-output skew [7] all outputs equally loaded 250 ps t 6 delay, ref rising edge to clkout rising edge [7] measured at v dd /2 0 350 ps t 7 device-to-device skew [7] measured at v dd /2 on the clkout pins of devices 0700ps t j cycle-to-cycle jitter [7] measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time [7] stable power supply, valid clock presented on ref pin 1.0 ms notes 5. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power up. power supply sequencing i s not required. 6. ref input has a threshold voltage of v dd /2. 7. parameter is guaranteed by design and characterization. not 100% tested in production. 8. all parameters specified with loaded outputs.
cy23s09, cy23s05 document number: 38-07296 rev. *g page 5 of 12 switching characteristics fo r cy23s05si-1h and cy23s09si-1h industrial temperature devices [8] parameter description test conditions min typ max unit t1 output frequency 30 pf load 10 pf load 10 10 100 133.33 mhz mhz duty cycle [7] = t 2 ? t 1 measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % duty cycle [7] = t 2 ? t 1 measured at 1.4 v, f out <50.0 mhz 45.0 50.0 55.0 % t3 rise time [7] measured between 0.8 v and 2.0 v 1.50 ns t 4 fall time [7] measured between 0.8 v and 2.0 v 1.50 ns t 5 output-to-output skew [7] all outputs equally loaded 250 ps t 6 delay, ref rising edge to clkout rising edge [7] measured at v dd /2 0350ps t 7 device-to-device skew [7] measured at v dd /2 on the clkout pins of devices 0700ps t 8 output slew rate [7] measured between 0.8 v and 2.0 v using te s t c i r c u i t # 2 1v/ns t j cycle-to-cycle jitter [7] measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time [7] stable power supply, valid clock presented on ref pin 1.0 ms switching waveforms figure 4. duty cycle timing figure 5. all outputs rise/fall time figure 6. ou tput-output skew figure 7. input-output propagation delay t 1 t 2 1.4 v 1.4 v 1.4 v output t 3 3.3 v 0 v 0.8 v 2.0 v 2.0 v 0.8 v t 4 1.4 v 1.4 v t 5 output output v dd /2 t 6 input output v dd /2
cy23s09, cy23s05 document number: 38-07296 rev. *g page 6 of 12 figure 8. device-device skew test circuits switching waveforms continued 2309?8 v dd /2 v dd /2 t 7 clkout, device 1 clkout, device 2 0.1 ? f v dd 0.1 ? f v dd clk out c load outputs gnd gnd 0.1 ? f v dd 0.1 ? f v dd 10 pf outputs gnd gnd 1 kw 1 kw test circuit # 1 test circuit # 2 for parameter t8 (output slew rate) on ?1h devices
cy23s09, cy23s05 document number: 38-07296 rev. *g page 7 of 12 ordering code definitions ordering information ordering code package name package type operating range pb-free CY23S05SXC-1 sz08 8-pin 150-mil soic commercial (0 ? to 70 ? c) CY23S05SXC-1t sz08 8-pin 150-mil soic ? tape and reel commercial (0 ? to 70 ? c) CY23S05SXC-1h sz08 8-pin 150-mil soic commercial (0 ? to 70 ? c) CY23S05SXC-1ht sz08 8-pin 150-mil soic ? tape and reel commercial (0 ? to 70 ? c) cy23s05sxi-1 sz08 8-pin 150-mil soic industrial (?40 ? to 85 ? c) cy23s05sxi-1t sz08 8-pin 150-mil soic ? tape and reel industrial (?40 ? to 85 ? c) cy23s09sxc-1 sz16 16-pin 150-mil soic commercial (0 ? to 70 ?? c) cy23s09sxc-1t sz16 16-pin 150-mil soic ? tape and reel commercial (0 ? to 70 ? c) cy23s09sxc-1h sz16 16-pin 150-mil soic commercial (0 ? to 70 ? c) cy23s09sxc-1ht sz16 16-pin 150-mil soic ? tape and reel commercial (0 ? to 70 ? c) cy23s09zxc-1h zz16 16-pin 4.4 mm tssop commercial (0 ? to 70 ? c) cy23s09zxc-1ht zz16 16-pin 4.4 mm tssop ? tape and reel commercial (0 ? to 70 ? c) tape and reel output drive: 1 = standard drive 1h = high drive temperature range: c = commercial i = industrial package: base device part number (s = spread aware) company id: cy = cypress 23s05 cy s(x) c 1(h) (t) 05 = 5-output zero delay buffer 09 = 9-output zero delay buffer s = soic, leaded z = tssop, leaded sx = soic, pb-free zx = tssop, pb-free -
cy23s09, cy23s05 document number: 38-07296 rev. *g page 8 of 12 package diagrams figure 9. 8-pin (150-mil) soic s08 and sz08 figure 10. 16-pin (150-mil) soic s16 and sz16 51-85066 *e 51-85068 *d
cy23s09, cy23s05 document number: 38-07296 rev. *g page 9 of 12 figure 11. 16-pin tssop 4.40 mm body z16 and zz16 package diagrams continued 51-85091 *d
cy23s09, cy23s05 document number: 38-07296 rev. *g page 10 of 12 acronym document conventions units of measure acronym description cmos complementary metal oxide semiconductor emi electromagnetic interference pll phase-locked loop soic small outline integrated circuit ss spread spectrum ssftg spread spectrum frequency timing generator ssop shrunk small outline package tssop thin shrunk small outline package symbol unit of measure ? c degree celsius mhz megahertz ua microamperes ma milliamperes ms milliseconds ns nanoseconds %percent pf picofarads ps picoseconds vvolt
cy23s09, cy23s05 document number: 38-07296 rev. *g page 11 of 12 document history page document title: cy23s09/cy23s05 low cost 3.3 v spread aware zero delay buffer document number: 38-07296 rev. ecn no. submission date orig. of change description of change ** 111147 11/14/01 dsg changed from spec number 38-01094 to 38-07296 *a 111773 02/20/02 ctk added 150-mil ssop option *b 122885 12/22/02 rbi added power-up requirements to operating conditions *c 267849 see ecn rgl added lead-free devices *d 2595524 10/23/08 cxq/pyrs added device ?status? to ordering information *e 2761988 09/10/09 kvm removed obsolete parts from ordering information table: cy23s09zc-1, cy23s09oc-1, cy23s09oc-1h, cy23s09zxc-1, cy23s09oxc-1, cy23s09oxc-1h. added CY23S05SXC-1t, CY23S05SXC-1ht, cy23s09sxc-1t, cy23s09sxc-1ht, cy23s09zxc-1ht. removed status column from ordering information table; added footnote. updated package names and added numerical temperature range to ordering information table. removed qsop package drawing. *f 2897373 03/22/10 cxq removed part numbers cy23s05sc-1, cy23s05sc-1h, cy23s09sc-1, cy23s09sc-1h, and cy23s09zc-1h from ordering information table. added cy23s05sxi-1 and cy23s05sxi-1t to ordering information table. updated package diagrams. updated copyright section. *g 3394655 10/04/11 puru added figure 1 updated hyper links updated package diagrams added ordering code definitions , acronym , and units of measure .
document number: 38-07296 rev. *g revised october 04, 2011 page 12 of 12 all product and company names mentioned in this document may be the trademarks of their respective holders. cy23s09, cy23s05 ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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